The present invention relates generally to the computer memory field and, more specifically, to methods and circuitry concerning programming elements of memory devices.
The fabrication and operation of electronic circuitry on a die often involves allowing for voltages or electronic signals to be received from sources external to the die by way of terminals on the die such as contact padsxe2x80x94electrically conductive areas that are relatively large in relation to a conductive line coupled thereto. The relatively large area of such pads allows them to receive voltages and signals from nodes such as bond wires or probe tips.
Concerning Dynamic Random Access Memory (DRAM) devices, for example, it is often desired to provide a pad that receives a voltage designated as xe2x80x9cDVC2.xe2x80x9d In normal operation, the DVC2 voltage is ideally half of the full voltage (Vcc) under which the memory device operates and which corresponds to a logic xe2x80x9c1xe2x80x9d value that may be stored in memory. The DVC2 voltage is applied to the DRAM""s digit lines, including the main digit lines as well as the complementary digit lines, before reading from or writing to a memory cell.
Writing to a memory cell further involves transmitting at least one command, such as a xe2x80x9cwrite enablexe2x80x9d (WE) signal, to the DRAM""s control circuitry. It is often desirable to provide a pad configured to receive the WE signal.
Moreover, operation of a DRAM may involve blowing an anti-fuse. Doing so may reroute a signal to or from a device other than the one originally configured to be associated with that signal. For example, in the event a defective memory cell is detected, an appropriate anti-fuse may be blown so that the relevant signals are associated with a redundant cell. Blowing an anti-fuse often involves generating enough of a voltage difference between the opposing plates of a capacitor to break down the dielectric between those plates. For instance, one plate may be coupled to a voltage source, herein referred to as CGND (also known as Vpop), while the other plate may be coupled to ground through a transistor. Thus, when CGND is applied to one plate and the transistor allows the other plate to be grounded for a sufficient time, a short is created between CGND and a node coupled to the other plate. Subsequently, the voltage of CGND is lowered and the transistor isolates the pathway to ground. As with the DVC2 voltage and the WE signal, a pad may be used to provide the CGND voltages. However, to provide yet another padxe2x80x94one dedicated to this purposexe2x80x94would require more die space and go against the desire in the industry to use as little space as possible per die in order fabricate more die on each silicon wafer. Further, providing such a pad would require more test resources per die, which decreases the ability to test in parallel and increases test time and cost. As a result, a pad that serves another function may be chosen to transmit the CGND voltage as well. Which pad is chosen depends on several factors.
Two factors to be considered in choosing the pad for CGND involve the notions that (1) blowing anti-fuses may be desired at several stages in the process of fabricating a memory device; and (2) some contact pads may not be available later in the process. The pad receiving DVC2, for example, is accessible for anti-fuse blowing that may occur during a production stage known as xe2x80x9cprobe.xe2x80x9d At that stage, testing an unpackaged die may occur by applying voltages directly to the die""s pads using conductive pins from a test device. However, at some point after probe, the die is packaged. As a non-limiting example of packaging, some of the contact pads may be bonded to wires leading to conductive fingers of a lead frame. The die is then encapsulated with a protective material, with the far ends of the fingers projecting from the encapsulant. Some of the contact pads, however, may not be bonded to wires and are therefore inaccessible after packaging. Nevertheless, additional testing, repairing, or reconfiguring of the die may be desirable at this stage, known as xe2x80x9cbackend.xe2x80x9d The DVC2 pad is a contact pad that is not bonded to a wire and is therefore inaccessible after packaging. As a result, one of ordinary skill in the art is encouraged to choose another pad to provide CGND.
A pad receiving the WE signal may be available during both probe and backend; but if a pad is accessible by a tester at backend in testing/reconfiguration modes, it may also be accessible by a post-production user during non-test/non-reconfiguration/standard operation modes. Because it is not desirable to allow such a user to affect CGND, the conductive path from the write pad to the anti-fuse must be regulated, such as with a transistor. However, in order to ensure that sufficient voltage passes through the transistor during an anti-fuse blowing mode at backend, self-booting circuitry is included. As discussed in greater detail below, such circuitry is not foolproof, and additional delays may be introduced into the anti-fuse blowing process.
As a result, there is a need in the art to address the time, methods and circuitry of blowing an anti-fuse.
Accordingly, exemplary embodiments of the current invention concern a direct connection between a die""s anti-fuse and a die terminal configured to receive an external voltage. In a preferred embodiment, the terminal is also configured to provide voltage to another device. When a voltage is being supplied to that other device, and that voltage would affect the ability of circuitry to properly determine the status of the anti-fuse, preferred embodiments of the current invention isolate the anti-fuse from such circuitry. In a more preferred embodiment, access to the terminal is eventually prevented, but access to the anti-fuse by way of a still-accessible second terminal is allowed, wherein the connection between the anti-fuse and the second terminal is regulated.